1 ? fn9155.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved all other trademarks mentioned are the property of their respective owners. isl6614 dual advanced synchronous rectified buck mosfet drivers with protection features the isl6614 integrates two is l6613 mosfet drivers and is specifically designed to drive two independent power channels in a multi-phase interleaved buck converter topology. these drivers combined with hip63xx or isl65xx multi-phase buck pwm controllers and n-channel mosfets form complete core-vol tage regulator solutions for advanced microprocessors. the isl6614 drives both the upper and lower gates simultaneously over a range from 5v to 12v. this drive- voltage provides the flexibi lity necessary to optimize applications involving trade-offs between gate charge and conduction losses. an advanced adaptive zero shoot-through pr otection is integrated to prevent both the upper and lower mosfets from conducting simultaneously and to minimize the dead time. these products add an overvoltage prot ection feature operational before vcc exceeds its turn-on threshold, at which the phase node is connected to the gate of the low side mosfet (lgate). the ou tput voltage of the converter is then limited by the thres hold of the low side mosfet, which provides some protection to the microprocessor if the upper mosfet(s) is shorted during startup. the over- temperature protection featur e prevents failures resulting from excessive power dissipation by shutting off the outputs when its junction temperature exceeds 150c (typically). the driver resets once its junction temperature returns to 108c (typically). the isl6614 also features a three-state pwm input which, working together with intersil?s multi-phase pwm controllers, prevents a negative transient on the output voltage when the output is shut down. this fe ature eliminates the schottky diode that is used in some systems for protecting the load from reversed output voltage events. applications ? core regulators for intel? and amd? microprocessors ? high current dc-dc converters ? high frequency and high efficiency vrm and vrd related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ? technical brief 400 and 417 for power train design, layout guidelines, and feedback compensation design features ? pin-to-pin compatible with hip 6602 soic family for better performance and extr a protection features ? quad n-channel mosfet drives for two synchronous rectified bridges ? advanced adaptive zero shoot-through protection - body diode detection - auto-zero of r ds(on) conduction offset effect ? adjustable gate voltage (5v to 12v) for optimal efficiency ? internal bootstrap schottky diode ? bootstrap capacitor ov ercharging prevention ? supports high switching frequency (up to 1mhz) - 3a sinking current capability - fast rise/fall times and low propagation delays ? three-state pwm input for output stage shutdown ? three-state pwm input hysteres is for applications with power sequencing requirement ? pre-por overvoltage +protection ? vcc undervoltage protection ? over temperature protection (otp) with 42c hysteresis ? expandable bottom copper pad for enhanced heat sinking ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free available ordering information part number temp. range (c) package pkg. dwg. # isl6614cb 0 to 85 14 ld soic m14.15 isl6614cb-t 14 ld soic tape and reel ISL6614CR 0 to 85 16 ld 4x4 qfn l16.4x4 ISL6614CR-t 16 ld 4x4 qfn tape and reel isl6614cbz * 0 to 85 14 ld soic (pb-free) m14.15 isl6614cbz-t * 14 ld soic tape and reel (pb-free) ISL6614CRz * 0 to 85 16 ld 4x4 qfn (pb-free) l16.4x4 ISL6614CRz-t * 16 ld 4x4 qfn tape and reel (pb-free) * intersil pb-free products employ special lead-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and lead-free soldering operations. intersil lead- free products are msl classified at lead-free peak reflow temperatures that meet or exceed the lead- free requirements of ipc/jedec j std-020b. contact the factory for availability. data sheet july 2004
2 isl6614 pinouts isl6614cb/isl6614cbz (soic) top view ISL6614CR/ISL6614CRz (16 lead qfn) top view pwm1 pwm2 gnd lgate1 1 2 3 4 14 13 12 phase1 ugate1 boot1 pvcc 1 2 10 9 8 7 6 5 boot2 ugate2 phase2 vcc pgnd lgate2 11 1 3 4 15 gnd lgate1 pvcc pgnd pwm2 pwm1 vcc phase1 16 14 13 2 12 10 9 11 6 578 ugate1 boot1 boot2 ugate2 nc lgate2 phase2 nc gnd block diagram for ISL6614CR, the pad on the bottom side of the qfn package must be soldered to the circuit?s ground. pre-por ovp features otp & vcc pwm1 +5v 10k 8k control logic shoot- through protection boot1 ugate1 phase1 lgate1 pgnd pwm2 10k 8k shoot- through protection boot2 ugate2 phase2 lgate2 +5v gnd pvcc pvcc pgnd pgnd pad channel 1 channel 2 pvcc pvcc
3 typical application - 4 channel converte r using isl65xx and is l6614 gate drivers main control isl65xx fb +5v comp pwm1 pwm2 isen2 pwm3 pwm4 isen4 vsen fs/dis isen1 isen3 gnd boot2 ugate2 phase2 lgate2 boot1 ugate1 phase1 lgate1 pwm1 pvcc 5v to 12v vcc dual driver isl6614 boot2 ugate2 phase2 lgate2 boot1 ugate1 phase1 lgate1 pwm1 pvcc vcc dual driver isl6614 v cc +v core pwm2 pwm2 en vid pgood +12v +12v +12v +12v +12v 5v to 12v +12v pgnd gnd pgnd gnd isl6614
4 absolute maximum rati ngs thermal information supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15v supply voltage (pvcc) . . . . . . . . . . . . . . . . . . . . . . . . . vcc + 0.3v boot voltage (v boot ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36v input voltage (v pwm ) . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 7v ugate. . . . . . . . . . . . . . . . . . . v phase - 0.3v dc to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lgate . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v dc to v pvcc + 0.3v gnd - 5v (<100ns pulse width, 2j) to v pvcc + 0.3v phase. . . . . . . . . . . . . . . gnd - 0.3v dc to 15v dc (v pvcc = 12v) gnd - 8v (<400ns, 20j) to 24v (<200ns, v boot-phase = 12v) esd rating human body model . . . . . . . . . . . . . . . . . . . . class i jedec std recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . . 0c to 85c maximum operating junction temperature . . . . . . . . . . . . . . 125c supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12v 10% supply voltage range, pvcc . . . . . . . . . . . . . . . . 5v to 12v 10% thermal resistance (typical notes 1, 2, 3) ja ( c/w) jc ( c/w) soic package (note 1) 90 n/a qfn package (notes 2, 3). . . . . . . . . . 46 8.5 maximum junction temperature (plastic package) . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effe ctive thermal conductivity test board in free air. 2. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 3. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, unless otherwise noted. parameter symbol test conditions min typ max units vcc supply current bias supply current i vcc f pwm = 300khz, v pvcc = 12v - 7.1 - ma gate drive bias current i pvcc f pwm = 300khz, v pvcc = 12v - 9.7 - ma power-on reset and enable vcc rising threshold 9.35 9.80 10.00 v vcc falling threshold 7.35 7.60 8.00 v pwm input (see timing diagram on page 6) input current i pwm v pwm = 5v - 450 - a v pwm = 0v - -400 - a pwm rising threshold vcc = 12v - 3.00 - v pwm falling threshold vcc = 12v - 2.00 - v typical three-state shutdown window vcc = 12v 1.80 2.60 v three-state lower gate falling threshold vcc = 12v - 1.50 - v three-state lower gate rising threshold vcc = 12v - 1.00 - v three-state upper gate rising threshold vcc = 12v - 3.20 - v three-state upper gate falling threshold vcc = 12v - 2.60 - v shutdown holdoff time t tsshd - 245 - ns ugate rise time t ru v pvcc = 12v, 3nf load, 10% to 90% - 26 - ns lgate rise time t rl v pvcc = 12v, 3nf load, 10% to 90% - 18 - ns ugate fall time t fu v pvcc = 12v, 3nf load, 90% to 10% - 18 - ns isl6614
5 lgate fall time t fl v pvcc = 12v, 3nf load, 90% to 10% - 12 - ns ugate turn-on propagation delay (note 4) t pdhu v pvcc = 12v, 3nf load, adaptive - 10 - ns lgate turn-on propagation delay (note 4) t pdhl v pvcc = 12v, 3nf load, adaptive - 10 - ns ugate turn-off propagation delay (note 4) t pdlu v pvcc = 12v, 3nf load - 10 - ns lgate turn-off propagation delay (note 4) t pdll v pvcc = 12v, 3nf load - 10 - ns lg/ug three-state propagation delay (note 4) t pdts v pvcc = 12v, 3nf load - 10 - ns output upper drive source current (note 4) i u_source v pvcc = 12v, 3nf load - 1.25 - a upper drive source impedance r u_source 150ma source current 1.4 2.0 3.0 ? upper drive sink current (note 4) i u_sink v pvcc = 12v, 3nf load 2 - a upper drive sink impedance r u_sink 150ma sink current 1.2 1.3 2.2 ? upper drive transition sink impedance (note 4) r u_sink_tr -1.32.2 ? upper drive dc sink impedance r u_sink_dc 150ma source current 0.9 1.65 3.0 ? lower drive source current (note 4) i l_source v pvcc = 12v, 3nf load - 2 - a lower drive source impedance r l_source 150ma source current 0.85 1.3 2.2 ? lower drive sink current (note 4) i l_sink v pvcc = 12v, 3nf load - 3 - a lower drive sink impedance r l_sink 150ma sink current 0.60 0.94 1.35 ? over temperature shutdown thermal shutdown setpoint - 150 - c thermal recovery setpoint - 108 - c notes: 4. guaranteed by design. not 100% tested in production. electrical specifications recommended operating conditions, unless otherwise noted. (continued) parameter symbol test conditions min typ max units isl6614
6 functional pin description package pin # pin symbol function soic dfn 1 15 pwm1 the pwm signal is the control input for the channel 1 driver. the pwm signal can enter three distinct states during operation, see the three-state pwm input section under description for further details. connect this pin to the pwm output of the controller. 2 16 pwm2 the pwm signal is the control input for the channel 2 driver. the pwm signal can enter three distinct states during operation, see the three-state pwm input section under description for further details. connect this pin to the pwm output of the controller. 3 1 gnd bias and reference ground. all signals are referenced to this node. 4 2 lgate1 lower gate drive output of channel 1. connect to gate of the low-side power n-channel mosfet. 5 3 pvcc this pin supplies power to both the lower and higher gate drives in isl6614. its operating range is +5v to 12v. place a high quality low esr ceramic capacitor from this pin to gnd. 6 4 pgnd it is the power ground return of both low gate drivers. - 5,8 n/c no connection. 7 6 lgate2 lower gate drive output of channel 2. connect to gate of the low-side power n-channel mosfet. 8 7 phase2 connect this pin to the source of the upper mosfet and the drain of the lower mosfet in channel 2. this pin provides a return path for the upper gate drive. 9 9 ugate2 upper gate drive output of channel 2. co nnect to gate of high-side power n-channel mosfet. 10 10 boot2 floating bootstrap supply pin for the upper gate driv e of channel 2. connect the bootstrap capacitor between this pin and the phase2 pin. the bootstrap capacitor provides t he charge to turn on the upper mosfet. see the internal bootstrap device section under descript ion for guidance in choosing the capacitor value. 11 11 boot1 floating bootstrap supply pin for the upper gate driv e of channel 1. connect the bootstrap capacitor between this pin and the phase1 pin. the bootstrap capacitor provides t he charge to turn on the upper mosfet. see the internal bootstrap device section under descript ion for guidance in choosing the capacitor value. 12 12 ugate1 upper gate drive output of channel 1. co nnect to gate of high-side power n-channel mosfet. 13 13 phase1 connect this pin to the source of the upper mosfet and the drain of the lower mosfet in channel 1. this pin provides a return path for the upper gate drive. 14 14 vcc connect this pin to a +12v bias supply. it supplies pow er to internal analog circuits . place a high quality low esr ceramic capacitor from this pin to gnd. - 17 pad connect this pad to the power ground plane (gnd) via thermally enhanced connection. isl6614
7 description operation designed for versatility and speed, the isl6614 mosfet driver controls both high-si de and low-side n-channel fets of two half-bridge power trains from two externally provided pwm signals. prior to vcc exceeding its por level, the pre-por overvoltage protection function is activated; the upper gate (ugate) is held low and the lower gate (lgate), controlled by the pre-por overvoltage protection circuits, is connected to the phase. once the vcc volta ge surpasses the vcc rising threshold (see electrical specif ications), the pwm signal takes control of gate transitions. a ri sing edge on pwm initiates the turn-off of the lower mosfet (see timing diagram). after a short propagation delay [t pdll ], the lower gate begins to fall. typical fall times [t fl ] are provided in the electrical specifications section. adap tive shoot-through circuitry monitors the phase voltage and determines the upper gate delay time [t pdhu ]. this prevents both the lower and upper mosfets from conducting simultaneously. once this delay period is complete, the upper gate drive begins to rise [t ru ] and the upper mosfet turns on. a falling transition on pwm results in the turn-off of the upper mosfet and the turn-on of the lower mosfet. a short propagation delay [t pdlu ] is encountered before the upper gate begins to fall [t fu ]. again, the adaptive shoot-through circuitry determines the lower gate delay time, t pdhl . the phase voltage and the ugate voltage are monitored, and the lower gate is allowed to rise after phase drops below a level or the voltage of ugate to phase reaches a level depending upon the current direction (see next section for details). the lower gate then rises [t rl ], turning on the lower mosfet. advanced adaptive zero shoot-through deadtime control (patent pending) these drivers incorporate a uni que adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower mosfets? body-diode conduction, and to prevent the upper and lower mosfets from conducting simultaneously. this is accomplished by ensuring either rising gate turns on its mosfet with minimum and sufficient delay after the other has turned off. during turn-off of the lower mosfet, the phase voltage is monitored until it reaches a -0.2v/+0.8v trip point for a forward/reverse current, at which time the ugate is released to rise. an auto-zero comparator is used to correct the r ds(on) drop in the phase voltage preven ting from false detection of the -0.2v phase level during r ds(on conduction period. in the case of zero current, the ugate is re leased after 35ns delay of the lgate dropping below 0.5v. during the phase detection, the disturbance of lgate?s falling transition on the phase node is blanked out to prev ent falsely tripping. once the phase is high, the advanced adaptive shoot-through circuitry monitors the phase and ugate voltages during a pwm falling edge and the subsequent ugate turn-off. if either the ugate falls to less than 1.75v above the phase or the phase falls to less than +0.8v, the lgate is released to turn on. three-state pwm input a unique feature of these driver s and other intersil drivers is the addition of a shutdown windo w to the pwm input. if the pwm signal enters and remains within the shutdown window for a set holdoff time, the driver outputs are disabled and both mosfet gates are pulled and held low. the shutdown state is removed when the pwm signal moves outside the shutdown window. otherwise, the pwm rising and falling thresholds outlined in the electrical specifications determine when the lower and upper gates are enabled. this feature helps prevent a negative transient on the output voltage when the output is shut down, eliminating the schottky diode that is used in some systems for protecting the load from reversed output voltage events. pwm ugate lgate t fl t pdhu t pdll t rl t tsshd t pdts t pdts 1.5v 8 in addition, more than 400mv hysteresis also incorporates into the three-state shutdown window to eliminate pwm input oscillations due to the capacitive load seen by the pwm input through the body diode of the controller?s pwm output when the power-up and/or power-down sequence of bias supplies of the driver and pwm controller are required. power-on reset (por) function during initial startup, the vcc voltage rise is monitored. once the rising vcc voltage exceeds 9.8v (typically), operation of the driver is enabled and the pwm input signal takes control of the gate drives. if vcc drops below the falling threshold of 7.6v (typica lly), operation of the driver is disabled. pre-por overvoltage protection prior to vcc exceeding its por level, the upper gate is held low and the lower gate is controlled by the overvoltage protection circuits during initial startup. the phase is connected to the gate of th e low side mosfet (lgate), which provides some protection to the microprocessor if the upper mosfet(s) is shorted during initial startup. for complete protection, the low side mosfet should have a gate threshold well below the maximum voltage rating of the load/microprocessor. when vcc drops below its por level, both gates pull low and the pre-por overvoltage protection circuits are not activated until vcc resets. internal bootstrap device both drivers feature an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes the boots trap circuit. the bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the trailing-edge of the phase node. this reduces voltage stress on the boot to phase pins. the bootstrap capacitor must have a maximum voltage rating above uvcc + 5v and its capacitance value can be chosen from the following equation: where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets per channel. the ? v boot_cap term is defined as the allowable droop in the rail of the upper gate drive. as an example, suppose two irlr7821 fets are chosen as the upper mosfets. the gate charge, q g , from the data sheet is 10nc at 4.5v (v gs ) gate-source voltage. then the q gate is calculated to be 53nc for pvcc =12v. we will assume a 200mv droop in drive voltage over the pwm cycle. we find that a bootstr ap capacitance of at least 0.267 f is required. gate drive voltage versatility the isl6614 provides the user flexibility in choosing the gate drive voltage for efficiency optimization. the isl6614 ties the upper and lower drive rails together. simply applying a voltage from 5v up to 12v on pvcc sets both gate drive rail voltages simultaneously. connecting a sot-23 package type of dual schottky diodes from the vcc to boot1 and boot2 can bypass the internal bootstrap devices of both upper gates so that the part can operate as a dual isl6612 driver, which has a fixed vcc (12v typically) on the upper gate and a programmable lower gate drive voltage. over temperature protection (otp) when the junction temperatur e of the ic exceeds 150c (typically), both upper and lower gates turn off. the driver stays off and does not return to normal operation until its junction temperature comes dow n below 108c (typically). for high frequency applications, applying a lower voltage to pvcc helps reduce the power dissipation and lower the junction temperature of the ic. this method reduces the risk of tripping otp. power dissipation package power dissipation is mainly a function of the switching frequency (f sw ), the output drive impedance, the external gate resi stance, and the selected mosfet?s internal gate resistance and total gate charge. calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of 125c. the maximum allowable ic power dissipation for the c boot_cap q gate ? v boot_cap -------------------------------------- q gate q g1 pvcc ? v gs1 ----------------------------------- - n q1 ? = (eq. 1) 50nc 20nc figure 2. bootstrap capacitance vs boot ripple voltage ? v boot_cap (v) c boot_cap ( f) 1.6 1.4 1.2 1. 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc isl6614
9 so14 package is approximatel y 1w at room temperature, while the power dissipation capacity in the qfn packages, with an exposed heat escape pad, is around 2w. see layout considerations paragraph for thermal transfer improvement suggestions. when designing the driver into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected mosfets. the total gate drive power losses due to the gate charge of mosfets and the driver?s internal circuitry and their corresponding average driver current can be estimated with eqs. 2 and 3, respectively, where the gate charge (q g1 and q g2 ) is defined at a particular gate to source voltage (v gs1 and v gs2 ) in the corresponding mosfet datasheet; i q is the driver?s total quiescent current with no l oad at both drive outputs; n q1 and n q2 are number of upper and lower mosfets, respectively; pvcc is the drive voltages for both upper and lower fets, respectively. the i q* vcc product is the quiescent power of the driver without capacitive load and is typically 200mw at 300khz. the total gate drive power losses are dissipated among the resistive components along t he transition path. the drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 and r gi2 ) of mosfets. figures 3 and 4 show the typical upper and lower gate drives turn-on transition path. the power dissipation on the driver can be roughly estimated as: layout considerations for heat spreading, place copper underneath the ic whether it has an exposed pad or not. the copper area can be extended beyond the bottom area of the ic and/or connected to buried copper pl ane(s) with thermal vias. this combination of vias for vert ical heat escape, extended copper plane, and buried planes for heat spreading allows the ic to achieve its full thermal potential. place each channel power component as close to each other as possible to reduce pcb copper losses and pcb parasitics: shortest distance between drains of upper fets and sources of lower fets; shortest distance between drains of lower fets and the power ground. thus, smaller amplitudes of positive and negative ringing are on the switching edges of the phase node. however, some space in between the power components is required for good airflow. the traces from the drivers to the fets should be kept short and wide to reduce the inductance of the traces and to promote clean drive signals. p qg_tot 2p qg_q1 ? 2p qg_q2 ? i q vcc ? ++ = (eq. 2) p qg_q1 q g1 pvcc 2 ? v gs1 -------------------------------------- - f sw ? n q1 ? = p qg_q2 q g2 pvcc 2 ? v gs2 -------------------------------------- - f sw ? n q2 ? = i dr q g1 n q1 ? v gs1 ----------------------------- - q g2 n q2 ? v gs2 ----------------------------- - + ?? ?? ?? f sw 2 ? i q + ? = (eq. 3) p dr 2p ? dr_up 2p ? dr_low i q vcc ? ++ = (eq. 4) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 2 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext1 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = figure 3. typical upper-gate drive turn-on path figure 4. typical lower-gate drive turn-on path q1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase pvcc pvcc q2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 isl6614
10 isl6614 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.4x4 16 lead quad flat no-lead plastic package (compliant to jedec mo-220-vggc issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.35 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 1.95 2.10 2.25 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 1.95 2.10 2.25 7, 8 e 0.65 bsc - k0.25 - - - l 0.50 0.60 0.75 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 5 5/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com isl6614 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not ex ceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m14.15 (jedec ms-012-ab issue c) 14 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 0 o 8 o 0 o 8 o - rev. 0 12/93
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